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Altera_Forum's avatar
Altera_Forum
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11 years ago

Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/vhdl/vhdlname_ela

When I was trying to synthesize following code: process(CLK) begin if rising_edge(CLK) then case find_1st_bit is when first => ...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Without examine the code in detail I'd like to as if it would be possible for you to try to compile this design in a newer version of Quartus than 11.0? I would expect such an internal error to be fixed by now if it is indeed something in the code that generates it.