Forum Discussion
AGarm
New Contributor
6 years agoHi,
I found a solution to the problem myself!
I used the external VHDL editor of the source text, because the Quartus editor does not work correctly with the Russian font.
When describing the signal
signal C1_ret_bits: std_logic_vector (4 downto 0);
I mistakenly used the Russian letter C.
But what is surprising is that the previous compilation of the project project was successful. This erroneous description of the signal did not immediately cause Quartus's internal error, but only with the next complication of my project.
I managed to localize the problem only after I saved the VHDL source code with the Quartus editor.