Internal CPU bus.

Hello,

Your question is very general, therefore it is difficult to answer.

In a NiosII-ARM-Risc processor architecture, data and instructions are transferred via a bus (Avalon Bus) to the CPU. The data can come from Rom Ram, UART or other components connected to the bus.

There the data ends up in a series of CPU-registers, then, operations are executed between the CPU registers. The result can be sent back to the memory or other components connected to the bus.

Depending on the type of processor, instructions & data can be cached. This means that if the cache contains the requested info, then the cache will provide.

However sometimes we do not want cached data, sometimes we want to read into a specific register each time (for example if we have an intelligent component such as a UART). In that case, using CPU instructions that never use cached data, we get the correct result.

Best Regards,

Johi.