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LKwia's avatar
LKwia
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8 years ago

Intel HLS 17.1 verilog code generation error.

If I have such a declaration of function: "hls_avalon_slave_component component void hls_aes256(hls_avalon_slave_memory_argument(1) uint8_t *control, hls_avalon_sl...
LKwia's avatar
LKwia
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8 years ago

I wrote aes in opencl, but in program "Intel® FPGA SDK for OpenCL 17.1 (aoc)" also generates errors.

set AOCL_BOARD_PACKAGE_ROOT=C:\intelFPGA\17.1\hld\board\c5soc

aoc -g0 -board=c5soc_sharedonly aes256.cl -o aes256

I will not upgrade to newer software (Quartus v18.0) because it has an unstable synthesis.

And now a very important question will appear:

Is it in your company, in addition to marketing, something does it still normally works ?