Intel HLS 17.1 verilog code generation error.

If I have a port declaration "hls_avalon_slave_memory_argument(16) uint8_t *in_data" then I should get a:

// AVS avs_in_data

input logic avs_in_data_enable,

input logic avs_in_data_read,

input logic avs_in_data_write,

input logic [3:0] avs_in_data_address,

input logic [7:0] avs_in_data_writedata,

input logic avs_in_data_byteenable,

output logic [7:0] avs_in_data_readdata,

output logic avs_in_data_readdatavalid.