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travisa
New Contributor
New ContributorIntegrating a stand alone DHL code with a IP in Quartus Prime Pro
Hi., I am working with Arria 10 GX FPGA board and Intel Quartus Prime Pro Edition Design Software Version 21.4 for Windows. I am trying to integrate a my own verilog code to the FIFO IP provided. ...
RichardT_altera
Super Contributor
Super ContributorYou can just Instantiating IP Cores in HDL.
The Quartus Pro does not support the Create Symbol Files for Current File. As design is getting bigger and complex, schematic design is not recommended. Please refer to the KDB below.
https://www.intel.com/content/www/us/en/support/programmable/articles/000086258.html
