Integer as an array.

Hi, read/understand the error and look at the code :cool:

remove temp0 form the line "signal temp0,temp1,temp2: integer :=0;"

add the line "signal temp : std_logic;" (from Tricky) just under

And write

temp <= to_signed(count, 1)(0);
HEX0 <= decode(temp0);

outside the process

OR write

process (clk) is
-- variable declarations
begin
if rising_edge(clk) then 
   count := count + 1;
    temp0 <= to_signed(count, 1)(0);
    HEX0 <= decode( temp0);
end if;
end process;

By this last way, you will produce register and then latence : count --> temp0 --> decode

(outside the "if rising_edge(clk)...end if;", you will get very unexpected results !)

You need to be more rigorous :-P and get good basis in VHDL (Altera vhdl style guide line....)