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ScottHu2021's avatar
ScottHu2021
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4 years ago

Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP

Dear, We are develop an application with FPGA 5CEFA5F23C8 based on Quartus Prime Standard 18.1. One problem occurred during instantiating DDR3 controller IP core： Our external memory is a DDR3...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Scott,


Do you have any update on this topic?


Thanks,

Adzim


  • ScottHu2021's avatar
    ScottHu2021
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi Adzim,

    we also monitored the signal "local_cal_success" exported from the controller interface which together with the "local_init_done" are high after power-on. So, the calibration and initialization process should succeeded.

    Regards,

    Scott