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ScottHu2021's avatar
ScottHu2021
Icon for New Contributor rankNew Contributor
4 years ago

Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP

Dear, We are develop an application with FPGA 5CEFA5F23C8 based on Quartus Prime Standard 18.1. One problem occurred during instantiating DDR3 controller IP core： Our external memory is a DDR3...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi Scott,


I'm not sure if you receive my latest feedback or not.

But I will post it again.

Sorry for any inconvenience.


The PLL reference clock may be assigned in the Address/Command I/O bank or in DQ I/O bank.

But for debugging flexibility, users are recommend to assign it in the Address/Command I/O bank.


Regards,

Adzim