Occasional Contributor
Regular ContributorHi,
Sorry for the delay. Please see my responses as following:
1)Please look into it and tell me what is the mistake I am doing and share the solution .qar file , where fitter is using just 1 DSP for 3 mult units.
[CP] For your information, I have sent you a updated QAR which fit your a.qar into 1 DSP builder. I am not sure what might be wrong with the existing logiclock assignment. However, I have deleted the existing regions and create a new region. Then, I assign the logic into the new region and Fitter is able to pass correctly.
2)How to give correct height and width for a logic lock region?
[CP] Normally I will perform the region selection directly at the Chip Planner. I am not really an expert into LogicLock and not very sure the method to give right height and width. We might need to further engage Software Team to further assist you if you would like to pursue on this.
3)Region_0 has 3 mult units, but what is the purpose of using region_1 ?
[CP] Sorry for any confusion. If I remember it correctly, one of the region is used for testing purpose. The right region should have only one DSP block inside.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
