Occasional Contributor
Regular ContributorHi,
For your information, I have attached a simple test design with 3 instances of 8x8 lpm_mult and use LogicLock to force packing into a single DSP block for your reference. You may refer to it and then apply to your own design. You may start with smaller amount of multiplier and then slowly expand the logiclock region.
Note that generally the recommendation would be to let Fitter to perform auto-fitting for your design instead of using LogicLock to pack the DSP. Fitter will select the right resources to fit your design.
Please let me know if there is any concern. thank you.
Occasional ContributorHi Chee Pin,
Below are my observations from the file you shared:
1) I found a.bdf with 3 copies of mult units.
2) Analysis was showing 3 DSP units usage, but fitter used just 1 DSP for 3 mult units because of logic_lock. So all well till this point.
Below are the changes I did in order to understand the logic-lock feauture :
1) changed mult type to signed , added 3 clock cycles latency to the IP.
2) instantiated the a.bdf in a_top.v, added a.sdc file.
Result after the changes:
1) fitter use to fail showing the error in logic_lock region. So I did this change region_0 or region_1 -> logic_lock region properties -> size and origin -> auto_fit
2) Now fitter is using 3 DSPs , which I dont want.
I am sharing new qar file.
1)Please look into it and tell me what is the mistake I am doing and share the solution .qar file , where fitter is using just 1 DSP for 3 mult units.
2)How to give correct height and width for a logic lock region?
3)Region_0 has 3 mult units, but what is the purpose of using region_1 ?
