Occasional Contributor
Regular ContributorHi,
Regarding your latest inquiries, please see my responses as following:
1) How can I use logic lock in quartus , to force fitter use limited DSPs?
[CP] Just to share on one of the method which I am aware of. At Quartus -> Tools -> Chip Planner, look for "Create LogicLock Region" button on the left side of the window. Click on it then select a region in the chip planner of where you would like to create a LogicLock region. You can try to select region with limited DSPs. Then go back to Project Navigator -> Hierarchy, look for the instances that you would like to assign to the previously created region. Right click on the instances -> LogicLock Region -> Assign to Existing LogicLock Region. You may then run through Fitter compilation.
2) What might be the performance in terms of frequency in both cases(32 DSPs and 48 DSPs) , if I force fitter to use limited DSPs?
[CP] As I understand it, the performance would be dependent on your design as well as compilation. Thus, you might need to compare after running compilation with the two designs on your side.
By the way, generally if you have sufficient DSP resources, it would be recommended to let the Fitter to perform auto-fitting instead of using LogicLock to pack the DSP builder.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
Occasional ContributorHi,
I tried using logic_lock method, like you suggested, but felt it was complex and couldnt achieve end result .
I am sharing archieve file (modules.qar)of my sample code.
Here I have instantiated 48 lpm_mult IP. Each lpm_mult takes two 8 bit inputs , and will provide 16 bit output.
Ideally tool should use 16 DSPs since each DSP in cyclone V has three 9x9 multipliers.
But it is using 24 DSPs(with each DSP using sum of two 18x18 multipliers)
If this is the case ,I will face shortage of DSPs in my top level.
So, I want the tool to use three 9x9 for each DSP(since i am only doing 8x8 multiplication).
1))I thought tool might be using more since its available, but it is not the case. Let me take a situation , Say If i instantiate 685 9x9 multipliers , It will use 342 DSPs(100 % usage- each DSP using sum of two 18x18), and for one more 9x9(i.e 685 th multiplier) it will use ALMs.
As a result there is drop in my required frequency . Tool should have used 3 9x9 atleast in this case since there are no more DSPs, to achieve required design right?But it is not happening.
2) Am I doing something wrong in the instantiation , so that tool is not understanding that it should use 1 DSP for 3 instances of 9x9 lpm_mults? If yes, please tell me how to make tool use it so?
3) I want to know how to use DSPs in different operational modes mentionaed in below document (page number 3-10)
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_5v2.pdf
