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Altera_Forum
Honored Contributor
Honored ContributorInstantiation Errors
Hello, I'm trying to reference my full adder module inside another module but seem to be getting lost somehow in the referencing. I keep getting the error Checker 'Full_Adder' not found. Insta...
Altera_ForumHonored Contributor
Honored ContributorHi,
The issue is the module names. Verilog is case sensitive. In the module you've used "Full_adder" and in the instantiation you've used "Full_Adder" . The tool will think this "Full_Adder " is another module. Just be careful about the module names. Plus as pointed out earlier, instances are not like C functions. Use named instances instead of positional as this will reduce the chances of errors.
