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Altera_Forum's avatar
Altera_Forum
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17 years ago

instantiating RAM and multiple instances

hi, Im new here and new to fpgas, verilog and quartus but learning fast. I have a question... I have written a program which requires data to be buffered from two ADCs. I have foudn a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

A module can have multiple instances. I previously overlooked that you said to use verilog, so a component definition isn't needed. But a verilog module instance as a VHDL component instance always has an module indentifier, that references the name of the module and an arbitrary instance identifier. For a RAM it's the same as for a simple logic gate (from an Verilog Tutorial): 

nand2 n1(in1, in2, out1);
nand2 n2(in3, in4, out2);