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Altera_Forum
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15 years ago

instaciating the same architecture twice gives different results

Hello everybody! I'm trying(!) to implement 2 OFDM transmitters in an Stratix III FPGA. I have one VHDL design for the transmitter. When I instanciate the design twice in the FPGA one of them w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

thanks kaz for the suggestions.

I already use a reset sequenzer that resets the design asynchronously and releases the reset synchronously. The resets of the different clock domains are released such that the next component starts to work after the previous has been reset.

where can I find this "don't care setting"? Does it affect only registers?

I've been using SignalTap to debug the design, but I recently removed it as it will alter the timing behavior and make fitting the design more difficult.

kind regards