Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi,
unfortunately I don't see a clear pattern, but I can tell that * resetting the design doesn't make a difference * when switching off and programming the FPGA again (same design) it sometimes works * compiling the design again SEEMS to effect which Tx works I know this is a very vague description, but this problem is really weird. At the moment I'm trying to create a floorplan for the design (LogicLock regions etc.) so that the components for one Tx are in one place. But for a well implemented design it shouldn't matter where the components are located, right? kind regards Christoph