Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

instaciating the same architecture twice gives different results

Hello everybody! I'm trying(!) to implement 2 OFDM transmitters in an Stratix III FPGA. I have one VHDL design for the transmitter. When I instanciate the design twice in the FPGA one of them w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

Hi GPK,

thanks for your fast response! I attached the entity where I instanciate the IFFT, cyclic prefix etc. the top level entity of the design, and also the SDC File for the timing constraints.

kind regards

Christoph

https://www.alteraforum.com/forum/attachment.php?attachmentid=2797

--- Quote End ---

Hi,

nothing strange found so far. Can you describe the misbehaviour a little bit more ?

Kind regards

GPK