Forum Discussion
Altera_Forum
Honored Contributor
17 years agoObviously, the data pins must have inout type and your design has to perform some multiplexing as in the example below (used for a static RAM):
IF Wave_RD = '1' THEN
RAM_nWEi <= '1';
RAM_Data <= "ZZZZZZZZZZZZZZZZ";
RAM_Adr <= Wave_Adr;
RAM_nOE <= '0';
RAM_nCE <= '0';
RAM_nLB <= '0';
RAM_nUB <= '0';
ELSIF Osc_WR = '1' THEN
RAM_nCE <= '0';
RAM_nOE <= '1';
RAM_nWEi <= '0';
RAM_nLB <= '0';
RAM_nUB <= '0';
RAM_Adr <= Osc_Adr;
RAM_Data <= Osc_Data;
ELSE
RAM_nCE <= '1';
RAM_nOE <= '1';
RAM_nWEi <= '1';
RAM_Data <= "ZZZZZZZZZZZZZZZZ";
END IF; The final RAM_nWE is formed by gating RAM_nWEi with phase shifted PLL clock to assure setup- and hold times for write data and addresses.