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Altera_Forum
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13 years ago

Initialize signal with random number

I'd like to intitialize one of my signals with a random number. The only way I know how to use random numbers in vhdl is with the UNIFORM statement in a testbench loop. Is there a way to assign a ran...
Altera_Forum's avatar
Altera_Forum
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13 years ago

You Can use the uniform function, but not in a process. It has to be used inside an initialisation function. But the problem is going to be the seeds need to come from somewhere, and Quartus wont let you store the seeds between function calls (theres no problem with this in VHDL per se via shared variables, but quartus doesnt like it). So you end up having to use a generic anyway.

So the answer is No for synthesisable code.