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FHint's avatar
FHint
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Info 276004 with ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON

Hello, I am trying to instantiate two RAM with a size defined by a generic g_desc_size. For this I use following statements in my VHDL code: attribute ramstyle : string; type ...
  • FHint's avatar
    FHint
    5 years ago
    Sorry, I only included the files that have direct impact on the problem and didn't check, whether the project was able to be built this way. But I have found the problem: the ST channel input port, that is connected to the read address of the RAM signal, was not driven by the ST source. Now that I have added logic in the source component RAM is being instanced. I still wonder why this was the cause though, because both RAM's read addresses mentioned above are driven by this ST channel input. Maybe it is because the one that worked is an asymmetrical RAM and Quartus handles them differently. Either way, it now works for both of them. Best Regards, Florian
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

Could you help to share your .qar design files so I could help to check on this?

  • FHint's avatar
    FHint
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi,

    thank you for the quick answer!

    Unfortunately I can not provide the whole project, but I added to the .qar all the files I think are necessary for the issue. (qsf, vhd, tcl, qsys)

    Best Regards,
    Florian

    • RichardT_altera's avatar
      RichardT_altera
      Icon for Super Contributor rankSuper Contributor
      5 years ago

      Could you help to confirm whether there is files missing in the qar?

      I can't run Analysis and Synthesis due to missing files. Not sure if I miss anything?
      Try to duplicate the issue with the qar that was provided to confirm that it is duplicable, before attaching a new one.

      Warning (12019): Can't analyze file -- file ../../core/ip/x_protocol/clhsPack.vhd is missing
      Warning (12019): Can't analyze file -- file ../../core/fpga_top/sib_nmi_clhs_fpga_top.vhd is missing

      • FHint's avatar
        FHint
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago
        Sorry, I only included the files that have direct impact on the problem and didn't check, whether the project was able to be built this way. But I have found the problem: the ST channel input port, that is connected to the read address of the RAM signal, was not driven by the ST source. Now that I have added logic in the source component RAM is being instanced. I still wonder why this was the cause though, because both RAM's read addresses mentioned above are driven by this ST channel input. Maybe it is because the one that worked is an asymmetrical RAM and Quartus handles them differently. Either way, it now works for both of them. Best Regards, Florian