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Altera_Forum
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16 years ago

Inferring ROM module

Hello everyone, I am currently designing 8-bit resolution Sinusoidal Wave Generator. I chose the look-up table method which needs a ROM module (256x8bit). I am using verilog coding and synthesize usi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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I think you need to add a clk.

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Exactly. View the Verilog language templates in Quartus editor, they have examples of RAM and ROM inference. The requirements are also explained in detail in the Quartus software handbook.