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Altera_Forum
Honored Contributor
14 years agoso just to close this thread off,
A single process version is this: --***************************************************** main : process (clock,StateMachine,StartWindow,TheInput,HannTable,PacketIndex,result,resultlv) begin if rising_edge(clock) then if(reset='1') then StateMachine <= idle; else case StateMachine is when newpacket => PacketIndex <= 0; StateMachine <= idle; when idle => if (StartWindow = '1') then StateMachine <= load; else StateMachine <= idle; end if; when load => --another surplus state StateMachine <= math1; when math1 => result <= TheInput*HannTable(PacketIndex); StateMachine <= math2; when math2 => resultlv <= std_logic_vector(to_signed(result,22)); StateMachine <= math3; when math3 => realout <= resultlv(21 downto 6); StateMachine <= math3; PacketIndex <= PacketIndex+1; when strobehigh => realoutstrobe <= '1'; StateMachine <= wait1; when wait1 => StateMachine <= wait2; when wait2 => StateMachine <= strobelow; when strobelow=> StateMachine <= waitend; realoutstrobe <= '0'; when waitend => if (PacketIndex = 64) then PacketIndex <= 0; StateMachine <= idle; elsif (StartWindow = '0') then StateMachine <= idle; PacketIndex <= PacketIndex; else StateMachine <= waitend; PacketIndex <= PacketIndex; end if; when others => StateMachine <= idle; PacketIndex <= 0; end case; end if; end if; end process; --***************************************************** -- so thanks again Kaz and Tricky It all seems obvious once you know