inferred latches in state machine \ general VHDL

Honored Contributor

14 years ago

Kaz,Tricky

thanks again for that, great help,

so an assignment at top, outside of the case would fix that,

but I do need to keep the value/s

so, as always seems to be the answer, wrapping the whole thing in the clock edge will be best ?

I can't help thinking in software and want to use a variable to back up and restore! will I ever be free of that mind set?

the phrase '2 process state machine' directed further study, I found this paper

which covers state machines in general, but very much in the context of VHDL . I would reccomend a read for beginners looking at state machines

Thanks again for your help

Pete B.

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