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Altera_Forum
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11 years ago

Inferred latch warning

Hi, When I write the following code: ENTITY test IS GENERIC ( DW: INTEGER := 4 ); ... clk, rst_n and other ports END ENTITY; ARCHITECTURE rtl OF test IS a: UNS...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Is the warning more a false warning? is the latch actually removed later during synthesis. Might be better off raising a case with altera mysupport to find out exactly why it does this.