--- Quote Start ---
Is it not because you have an asynchronous reset for a? this means the register is removed but it still has a reset assignment - hence a transparent latch.
--- Quote End ---
You are right. But maybe I wasn't clear enough: there are NO latches inferred here, but the warning is issued nonetheless.
I see no easy way of telling the compiler that it should not reset the bits for which it eventually optimizes away the registers. In the meantime, I tried several things:
- use an (OTHERS => '0') initialization on a does not work;
- dropping the IF rst_n ='0' clause altogether works, but doesn't seem such a good idea;
- creating and using a synchronous reset signal does not work;
- dropping the IF rst_n ='0' and using the synchronous reset in the clocked process section works, but a MUX is inferred and the zero a lines become registers again.
Honored Contributor
