Induced delay

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You can use simple 16 or 32 bit counter and output of this counter can be assigned to your output.For example,we can divide a frequency by 8 using 3 bit counter.You can assign msb of counter to your output which will stay high for four clock cycle and low for four clock cycle.

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The problem with that would be the low frequency I require .

My final time requirement ranges from 30 sec to 30 minutes.

I changed the code to the following , which still gives OUTPUT as always HIGH.

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.all;

entity timernew is

port (clk : in std_logic;

flag : out std_logic:='0' );

end timernew;

architecture behavioral of timernew is

begin

process(clk)

variable count : integer:=0;

variable count1: integer:=0;

constant int: integer :=(10**6);

begin

if(clk'event and clk='1') then

count := count +1; --increment counter.

end if;

if count = int then

count := 0;

else

count := count + 1;

end if;

if count1 > 1000 then flag <= '1' ;

end if;

end process;

end behavioral;