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Altera_Forum
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13 years ago

Increasing fmax performance.

Hello. I have two subdesigns in my project working at 50MHz and 143MHz respectively. They both share sdram working at 143MHz so the design is something like subsys1->pipeline bridge->clock crossin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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And what can You see in the Fmax report?

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fmax for this clock is something around 140MHz. I think it'll rather work on the real hardware (worst case slack is -0.051 in slow model simulating) but it is not seem to be right. Also, i did not found any specification on how vip components are implement in Cyclone 2/3/4, the only information is for Cyclone V and Starix V. Does this mean it is not guaranteed to work on those chips?

josyb

Sounds pretty reasonable :(