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Altera_Forum's avatar
Altera_Forum
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13 years ago

Increasing fmax performance.

Hello. I have two subdesigns in my project working at 50MHz and 143MHz respectively. They both share sdram working at 143MHz so the design is something like subsys1->pipeline bridge->clock crossin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I faced the same issue: the FMax of the system is dominated by those pesky burst-adapters. This module is obviously poorly designed. As Qsys boasts itself as being a Message-Oriented design, there is no excuse for the long combinatorial chain. Of course if you test on the fastest and latest Stratix components this is not readily apparent, but on a Cyclone IV speed grade 8 system, the low cost ones :cry:, it hurts.