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SCAND2's avatar
SCAND2
Icon for New Contributor rankNew Contributor
7 years ago

Incorrect FPGA speed grade in "Stratix 10 external memory interfaces" IP core (Quartus Prime Pro 17.1)

Hi, at the end of the synthesis of a design based on a Stratix 10 GX Development kit I get the critical warnings in the figure. The speed grade defined in the IP is the wrong one. I'm facing the e...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Yes, we confirm that this critical warning can be safely ignore.

This issue is fixed in 18.0 and above.

I tried the same step in 18.0 and this critical warning is removed.

*18.0 do not support device with suffix S1 (engineering sample 1), so I used S2.