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SCAND2's avatar
SCAND2
Icon for New Contributor rankNew Contributor
7 years ago

Incorrect FPGA speed grade in "Stratix 10 external memory interfaces" IP core (Quartus Prime Pro 17.1)

Hi, at the end of the synthesis of a design based on a Stratix 10 GX Development kit I get the critical warnings in the figure. The speed grade defined in the IP is the wrong one. I'm facing the e...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi Samuele,

May I know what is your targeted device? I check on Quartus Pro 17.1 B240, the device with OPN-1sg280lu3f50e3vgs1 is supported.

I tried generate EMIF IP using this OPN in QII Pro 17.1 and perform compilation. I am still get this critical warning. From EMIF perspective both E3 and E3V speed grade is same.

Quartus give this warning because the IP still using old timing model (E3V) but latest quartus 17.1 (non Beta version) already have some timing model upgrade and it treat E3V and E3 as different model. So, it issue this false alarm.

So, I believe this critical warning can be safely ignore. I will check with development team to double confirm and get back to this thread again.

Last but not least, if you are generate the IP in beta version, I will suggest you to re-generate it again in non beta version.

Thanks

BC