Including UniPHY IP for DDR2 in project

Hello,

I am currently trying to incorporate a generated PHY layer into one of my projects. I generated the IP in QSYS and was able to test run a project done in the Quartus GUI. However, I am trying to include the necessary files in the .tcl file for my actual project. I added the .qip file, which I had believed was all I needed, to the .tcl file like so:

set_global_assignment -name SEARCH_PATH ../bfds/synthesis

set_global_assignment -name MISC_FILE PHY.qip

However, I am getting this error:

Error (12006): Node instance "mem_if_ddr2_emif_0" instantiates undefined entity "PHY_mem_if_ddr2_emif_0" File: /home/delatorre/MultAddStream_PROCStarIV_4FPGA_Memory2/bfds/synthesis/PHY.vhd Line: 109

The mem_if_ddr2_emif_0 file is included in the .qip file and is present in the submodules folder that is in the folder in which the PHY.vhd and PHY.qip file reside. All of the files in question are generated by QSYS and have not been touched by me at all.