Including Files in Verilog

Hi Mike,

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I tried:

set my_path file join root_of_path tail_of_path

set_global_assignment -name VERILOG_FILE $my_path

This has no effect. I tried it with just the path, and with the file name.

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There's examples of how to script Quartus in this tutorial:

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

If you look at one of the synthesis scripts, eg.,

altera_jtag_to_avalon_mm_tutorial\hdl\boards\bemicro_sdk\qsys_system\scripts\synth.tcl

you'll see an example of how the script determines the path to the tutorial source, and then uses absolute paths in the subsequent assignments.

Cheers,

Dave