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Altera_Forum's avatar
Altera_Forum
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13 years ago

Including Files in Verilog

I am a noob at Quartus. I have a large chunk of a very large ASIC design that I want to implement in an FPGA. The design to be implemented is spread across several directories. I cannot get ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I tried:

set my_path file join root_of_path tail_of_path

set_global_assignment -name VERILOG_FILE $my_path

This has no effect. I tried it with just the path, and with the file name.

Mike