SparkyNZ
Contributor
5 years agoIncluding files in Quartus II 14.x Project without compiling
I can include Verilog code within a Verilog file (e.g. File1.sv) using the following:
`include "File2.sv"
Unfortunately, if I have the above File2.sv file in the Files tree of Project Navigator, Quartus will try and compile it.
How can I add a file to my project so that it will not compile? (I only want it to be included and compiled within File1.sv and I would like to keep File2.sv as a seperate file to make the code easier to manage)