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Altera_Forum
Honored Contributor
16 years agoIn my application, I have a Source&Probe parallel interface (address, data, r/w and manual override of regular function) to the respective components in the production design. But it's an FPGA, where a few ten multplexers and registers don't count. I see a problem with short resources in EPM240.
If not needed repeatedly, a different configuration could be programmed to the MAX II for initial memory programming. The lowest resource count and most effective operation could be achieved with a Virtual JTAG function similar to SFL (serial flash loader), that streams multiple JTAG bits in one shift action directly to the memory. SFL is not enabled for MAX II by the Megawizard, but the sources are present in the library folder. I still think, that the said generic boundary scan method is most simple to implement, cause it doesn't depend on undocumented Altera interfaces. Commercial and public domain tools should be available.