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Altera_Forum
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17 years ago

in-system memory read in VHDL

Hi Freinds I'm using QuartusII7.2 and interested in having a ROM in my project using in-system memory(do not use logic cell), i created Hexadecimal (Intel-Format) File and initialized that but i d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I thought of something like below (with an array variable for the addresses). I saw, that you have APEX II, which has an asynchronous RAM/ROM, different from all newer FPGA types. 

genrom:
for i in 1 to 10 generate
tcgrom: lpm_rom
generic map ( lpm_widthad => 7,
lpm_outdata => "unregistered",
lpm_address_control => "unregistered",
lpm_file => "table.hex", -- init data
lpm_width => 14)
port map ( address => prm(i), q => ttfs(i));
end generate;