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Altera_Forum
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13 years ago

Improving Fitter Routing

Hi, I am trying to fit an exponentiation algorithm which processes data of widths 4K bits at a time on a cyclone 2 chip. The number of logic elements are currently within the device specificat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Yes. The system has a lot of combinatorial logic. I am not able to reduce them as of now. I am not familiar with pipelining in FPGA and logic lock regions but I will surely look at them. Thanks for your suggestions.