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Altera_Forum
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17 years ago

Implementation and Timing of Reset Circuits

Most circuit designs employing FPGAs and ASICs are synchronous systems using a large number of flip-flops or registers. It is usually important that these synchronous elements are capable of startin...
Altera_Forum's avatar
Altera_Forum
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17 years ago

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The chip-wide reset is called DEV_CLR, and is seldom used by designers. It will asynchronously reset every register in the device, whether it is used or not. It will not respect your code in that if you have register that you want to be HI after reset instead of LO, it will not do that. It will also not respect the power-up setting for registers that would allow you to have a register power-up HI.

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Hmm, isn't power-up to high level implemented as NOT gate push-back? Wouldn't this mean that DEV_CLR would respect your power-up setting?