Implementation and Timing of Reset Circuits

Hi all,

As a side note related indirectly to reset issues:

One way of having a good design practice - when possible - is to use design synchronisation approach so that if things go wrong then the circuit will auto-recover.

Beginners usually depend too much on start-up conditions and in many cases their modules are passed over to new projects causing serious problems.

Synchronisation, here, refers to the events themselves not the clock.

For example, somebody may design all processing of a stream depending entirely on first stream head...yet a better design is to redetect headers every frame or block ...etc and resynchronise accordingly. This includes state machines as well. This guarantees a trouble free flow.

kaz