Implementation and Timing of Reset Circuits

Actually, I am the author of this paper, so I will respond.

The circuit in Fig. 16 is the standard way that is used for many FPGA applications (or Fig. 20 if a PLL is involved) and is quite robust.

The implementation of the LAB-wide synchronous clear is shown in Fig. 3, and it IS gated with the data as indicated by the red circle.

The chip-wide reset is called DEV_CLR, and is seldom used by designers. It will asynchronously reset every register in the device, whether it is used or not. It will not respect your code in that if you have register that you want to be HI after reset instead of LO, it will not do that. It will also not respect the power-up setting for registers that would allow you to have a register power-up HI. Since it is an asynchronous reset, it will not take the registers out of reset synchronously to your clock(s), so it would seem that it would only be useful for single clock designs where it would have to be synchronized external to the FPGA. You can see why it is not usually used by many designers. (Also note that it will not reset the program memory, so the device does not need to be reprogrammed after DEV_CLR is asserted).