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CBrow36's avatar
CBrow36
Icon for New Contributor rankNew Contributor
6 years ago

I'm wondering is whether there is a way to generate or not generate the jbc file based on an environment variable. Any ideas? I'd like to not create a jbc when I don't generate ALTPLL to speed simulation.

What started as a design workaround when I found that ALTPLL in Verilog was broken is also useful in simulation. I feed an external clock into the simulator and don't instantiate the PLL and it runs...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

The easiest thing would be to not have the Assembler, which generates the file, run during a full compilation. In the Pro edition, you can click a checkbox in the Compilation Dashboard, but in the Lite edition, go to Project menu -> Settings -> Compilation Process Settings and turn off "Run Assembler during compilation."

When you do need to generate the file, just run the Assembler manually from Processing menu -> Start -> Start Assembler.

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