IM NEWBIE TO QUARTUS PRIME 18.1, export MAX 10 ADC conversion data to the core for post-processing, FOLLOWING THIS TUTORIAL SO OCCURING SOME PROBLEMS....

Question

Error (170084): Can't route signal "modular_adc_0_adc_pll_clock_clk~input" to atom "daff1_adc:adc|altera_modular_adc_control:control_internal|fiftyfivenm_adcblock_top_wrapper:adc_inst|fiftyfivenm_adcblock_primitive_wrapper:adcblock_instance|primitive_instance"

AND

Error (171000): Can't fit design in device

THIS SHOWS WHEN I START ( FITTER ( PLACE & ROUTE) )......

vicky1 · Answer

Hi,I request you, please open new thread for better support &amp; tracking purpose.Help me to close this thread if you have resolved the issue with our support.Regards,Vicky

vicky1 · Answer

Hi,Which tutorial are you going through?Would you like to provide project (*qar)file('Project ' Menu-&gt;'Archive Project') for replication of issue?Regards,Vicky

eshuk · Answer

https://www.youtube.com/watch?v=u7y5ZR1E8SU please go through above link....im working on altera max 10 fpga board...

vicky1 · Answer

Hi,Please check the '*.qar' available in below link, If in case it is required to upgrade, first upgrade it https://forums.intel.com/s/createarticlepage?articleid=a3g0P0000005Rc9QAE&amp;artTopicId=0TO0P000000MWKBWA4&amp;action=view You can also check the attached  .qar upgraded in Q18.1 Lite. Please let me know if you have any different concern.Regards,Vicky

eshuk · Answer

THANK YOU, NOW I GET IT WHERE'S THE PROBLEM WAS...

Forum Discussion

IM NEWBIE TO QUARTUS PRIME 18.1, export MAX 10 ADC conversion data to the core for post-processing, FOLLOWING THIS TUTORIAL SO OCCURING SOME PROBLEMS....

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