Ignoring timing violations

You could use the cut timing path setting but I assume there is still some timing requirement.

Perhaps the multi-cycle path option is more appropriate whereby you constrain a path between nodes to a number of clock cycles.

I usually use the "Locate in Assignment Editor" option and search for the node in "Design Entry". Are you certain that the pins you are looking for are not being optimized away? i.e. this can happen if they are inputs and do not drive any logic that effects an output. Then you may see the 'No element named x was found in the netlist' message.

Hope this is of some help