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Altera_Forum's avatar
Altera_Forum
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16 years ago

Ignoring timing violations

Hello everyone,

I need help with setting some timing constraints. I have high frequency data lines which are constrained with 275MHz clock. Also, I have another input signals which work with the same frequency but are not crucial for the design and the constraints can be violated. How shall I set the fitter to ignore optimization of these lines and classic timing analyzer to disable warnings ? Is maybe the "Cut Timing Path" setting appropriate in this case ?

And one more question. When I set the timing constraints, how shall i find appropriate node's names to assign the constraint ? I'm doing it from RTL wiever->Locate in Assignment Editor but Timing Analyzer often ignores the node saying i.e. 'No element named x was found in the netlist'.

Best Regards

Joel

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    You could use the cut timing path setting but I assume there is still some timing requirement.

    Perhaps the multi-cycle path option is more appropriate whereby you constrain a path between nodes to a number of clock cycles.

    I usually use the "Locate in Assignment Editor" option and search for the node in "Design Entry". Are you certain that the pins you are looking for are not being optimized away? i.e. this can happen if they are inputs and do not drive any logic that effects an output. Then you may see the 'No element named x was found in the netlist' message.

    Hope this is of some help