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Altera_Forum
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13 years ago

if Clock 50MHz, how many ns used is appropriate for behavior vhdl ?

if Clock 50MHz, what is the maximum ns in after X ns can be used is appropriate for behavior vhdl ? for example http://www.people.vcu.edu/~rhklenke/tutorials/vhdl/modules/m12_23/sld006.htm
Altera_Forum's avatar
Altera_Forum
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13 years ago

because data are continously receive like a flow or stream and then algorithm and send. sending ethernet frame occupy many cycles, i wish to make algorithm involve in it. actually i do not know how many average cycles of an algorithm occupy in FPGA chip,

if can not do algorithm within cycles of sending ethernet header before send a payload, there is only one choice that do it sequentially which is to finish algorithm first then send ethernet frame

is the clock cycle in ethernet frame 1/(50 * 10^6) = 0.00000002 = 20 ns ? if sending ethernet frame using 8 * 20ns, can an algorithm run within 8 * 20 ns?