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Altera_Forum
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13 years ago

if Clock 50MHz, how many ns used is appropriate for behavior vhdl ?

if Clock 50MHz, what is the maximum ns in after X ns can be used is appropriate for behavior vhdl ? for example http://www.people.vcu.edu/~rhklenke/tutorials/vhdl/modules/m12_23/sld006.htm
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Altera_Forum
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13 years ago

But you know how long it will take - 1 clock cycle (though that seems rather short for "an algorithm"). So why do you need a delay? delays need to be in numbers of clocks, not fixed time delays. Digital circuits do not work like that.