New Contributor
ContributorHi, Your design is accessing SDA from different (unnamed) processes.
So write SDA just in one process, in case signal from one process to other what to do on SDA.
Curing this, can work anyway but you are not guaranteed external devices are high state. To avoid contention, never drive SDA nor SCK High, drive 'Z' or '0'.
FPGA work better on syncronous design, avoid ripple carry or clock crossing domain, generate enable instead.
it is optional but is better style name every process with a name. This can help identify logic and help read code:
example U1_SCK_edge_detect : process(clk, reset)
On my old books where written to avoid elsif rising_edge, goggling around also college site I seen a lot of example using
if reset then
elsif rising_edge(clk) thenThis was discouraged on old school with nested if then else instead of if then elsif:
[processname:] process(clk,reset)
begin
if reset then
{reset action}
else
if risng_edge(clk) then
[if clk_enable then else end if]
end if;
end if;
end process;
Aout this no idea if exhibit side effect.
If this cannot solve your issue ask again.
Regards
