I2C Controller

-------------------------------------------------------------------------------

-- Port Declarations --

-------------------------------------------------------------------------------

entity I2C_Controller is

GENERIC(

input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz

bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz

port (

-- Inputs

clk : in std_logic;

reset_n : in std_logic;

address : in std_logic_vector (2 downto 0);

we : in std_logic;

byte_enable : in std_logic_vector (1 downto 0);

rd : in std_logic;

data : in std_logic_vector (31 downto 0);

-- Bidirectionals

I2C_SDAT : inout std_logic;

-- Outputs

acknowledge : out std_logic;

I2C_SCLK : out std_logic;

read_data : out std_logic_vector (31 downto 0);

--SRAM_ADDR : out std_logic_vector (17 downto 0);

--SRAM_CE_N : out std_logic;

--SRAM_WE_N : out std_logic;

--SRAM_OE_N : out std_logic;

--SRAM_UB_N : out std_logic;

--SRAM_LB_N : out std_logic

);

end I2C_Controller;

architecture I2C_Controller_rtl of I2C_Controller is

CONSTANT Period_Count : INTEGER := "126";

CONSTANT HALF_PERIOD_COUNT : INTEGER := "63";

type State_type is (idle,reads,writes);

signal current_state, next_state: state_type;

begin

process(clk,reset_n)

VARIABLE count : INTEGER RANGE 0 TO divider*4;

begin

if (reset_n = '0') then

current_state <= idle;

elsif (clk'event and clk = '1') then

current_state <= next_state;

end if;

end process;

process(bus_enable,rw,current_state,address,I2C_SDAT,write_data)

begin

case current_state is

when idle =>

acknowledge <= '0';

SRAM_CE_N <= '1';

SRAM_OE_N <= '1';

SRAM_WE_N <= '1';

read_data <= (others => 'Z');

SRAM_ADDR <= (others => '0');

I2C_SDAT <= (others => 'Z');

if (bus_enable = '1') then

if (rw = '1') then

next_state <= reads;

else

next_state <= writes;

end if;

end if;

when reads =>

SRAM_ADDR <= address (17 downto 0);

SRAM_CE_N <= '0'; --chip enabled

SRAM_OE_N <= '0'; --read enabled

SRAM_WE_N <= '1'; --write disabled

read_data <= I2C_SDAT;

I2C_SDAT <= (others => 'Z');

acknowledge <= '1';

next_state <= idle;

when writes =>

SRAM_ADDR <= address (17 downto 0);

SRAM_CE_N <= '0'; --chip enabled

SRAM_OE_N <= '1'; --read disabled

SRAM_WE_N <= '0'; --write enabled

I2C_SDAT <= write_data;

read_data <= (others => 'Z');

acknowledge <= '1';

next_state <= idle;

end case;

end process;

process(byte_enable)

begin

if byte_enable = "00" then

SRAM_UB_N <= '1';

SRAM_LB_N <= '1';

elsif byte_enable = "01" then

SRAM_UB_N <= '1';

SRAM_LB_N <= '0';

elsif byte_enable = "10" then

SRAM_UB_N <= '0';

SRAM_LB_N <= '1';

else

SRAM_UB_N <= '0';

SRAM_LB_N <= '0';

end if;

end process;

end I2C_Controller_rtl;