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Austin_7's avatar
Austin_7
Icon for New Contributor rankNew Contributor
5 years ago

I want to solve 'top level design entity is undefined' problem. Please help me.

I'm the student and the beginner at FPGA. I found some people who had the same problem. I think I checked what they did, but the problem still exists. Please help me. I uploaded one minute video. S...
Austin_7's avatar
Austin_7
Icon for New Contributor rankNew Contributor
5 years ago

I really appreciate your help. After I changed my module name, the different error which you said occurred.

"Error (12061): Can't synthesize current design -- Top partition does not contain any logic"

The code was from the first part of the book and I think I really have to change the book to study,,,

Thank you.

RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

안녕하세요!

Since you are starting to design FPGA, you may checkout the course below as a starting point.

How to Begin a Simple FPGA Design

After that, you may checkout the webpage below to further explore courses that you are interested to learn. (fyi: How to Begin a Simple FPGA Design course is under FPGA Designers - level 200)

https://www.intel.com/content/www/us/en/programmable/support/training/curricula.html

Hope it helps in your FPGA journey.