New Contributor
Super ContributorThe module in your HDL is named "hello" which doesn't match what you've specified as the top-level entity ("2_2_Hello_Word"). Either change the HDL code or the name of the top-level entity in the project settings.
Also note that none of that HDL code in 2_2_Hello_Word.v is synthesizable so compiling it in Quartus isn't going to do anything. The code you've written is more like what would be a simulation testbench for a simulation tool like ModelSim.
New ContributorI really appreciate your help. After I changed my module name, the different error which you said occurred.
"Error (12061): Can't synthesize current design -- Top partition does not contain any logic"
The code was from the first part of the book and I think I really have to change the book to study,,,
Thank you.
Super Contributor안녕하세요!
Since you are starting to design FPGA, you may checkout the course below as a starting point.
How to Begin a Simple FPGA Design
After that, you may checkout the webpage below to further explore courses that you are interested to learn. (fyi: How to Begin a Simple FPGA Design course is under FPGA Designers - level 200)
https://www.intel.com/content/www/us/en/programmable/support/training/curricula.html
Hope it helps in your FPGA journey.
